Desktop | Mobile
Wednesday, November 14, 2007, 07:50 AM JST
Posted by Yanto Suryono
If you have been doing hardware design using Verilog and/or VHDL, and use VHDL to build testbench, I think you will agree with me, that it is nice if you can refer to any signal in any module beneath the testbench module similar to what Verilog can do.

When doing hardware verification, usually we put the design under test (DUT) in a testbench module. The testbench module generates stimuli for the DUT, captures signals from the DUT and then evaluates it. In the process of capturing signals, if the signals appear at the DUT ports, then it is fine, because it is directly visible at testbench hierarchy.

However, if the signals is the internal ones, which are normally not needed to be output by the DUT, then we have problem, especially if our design is a complex mixed HDL design. There are many reasons for the need to capture internal signals, not only visually check them on the waveform viewer. One obvious one is if we need to dump the signals to a file for further processing but we want to keep our module HDL clean from debug/test codes.

Basically, what we need here is a method to map any signal through the design hierarchy to a signal in or visible to the testbench.

Fortunately, most modern HDL simulators support exactly what we need here, at least for the two simulators I have been using : Cadence NC-SIM and Synopsys VCS-MX.

Cadence NC-SIM has NC-MIRROR, while Synopsys VCS-MX has XMR, and both of them provides the same functionality. All you have to do is to use the vendor specific libraries, and instance a specific module to map any signal in the design by specifying its path to a signal in the module. The beauty is, the path can cross both Verilog and VHDL hierarchies without problem.

The example below shows how to map signal signal1 in u_verilogmod instance, which is inside U_VHDLMOD1 VHDL instance inside U_DUT VHDL design top. The U_DUT is instantiated in TESTBENCH entity of testbench and the mapping destination is signal1_mapped_w.

Cadence NC-MIRROR:

library NCUTILS;
use NCUTILS.ncutilities.all;

nc_mirror("signal1_mapped_w", ":U_DUT:U_VHDLMOD1:u_verilogmod:signal1", "");

Synopsys XMR:

library SYNOPSYS;
use SYNOPSYS.HDL_XMR_PKG;

hdl_xmr("/TESTBENCH/U_DUT/U_VHDLMOD1/u_verilogmod/signal1", "signal1_mapped_w");


Even if Verilog portion of the signal path includes backslash prepended name, there is no problem:


Cadence NC-MIRROR:

library NCUTILS;
use NCUTILS.ncutilities.all;

nc_mirror("some_req_0_q_w", ":U_DUT:U_VHDLMOD1:\verilog/backslashed/prepended/path/some_reg[0] :Q", "");

Synopsys XMR:

library SYNOPSYS;
use SYNOPSYS.HDL_XMR_PKG;

hdl_xmr("/TESTBENCH/U_DUT/U_VHDLMOD1/\verilog/backslashed/prepended/path/some_reg[0] /Q", "some_req_0_q_w");


Note that the destination module does not have to be the testbench top. Usually I make a special module inside testbench for this task. The big reason for doing so is because the mapping functionality is vendor specific and I do not want to rewrite my whole testbench whenever I need to switch simulator. By making it a special module, I just need to rewrite that single module when I switch simulator.

Happy Designing !


Leave a Comment

Fields with * are required.